(1) Field of the Invention
The present invention relates to methods for fabricating a semiconductor device in which copper is used for interconnects or plugs.
(2) Description of Related Art
With a recent CMOS miniaturization, the interconnect resistance has been increasing markedly due to miniaturization of interconnects. An increase in the interconnect delay time due to an increase in the interconnect resistance leads to degradation in the LSI performance. For this reason, the need for reducing the interconnect resistance has become imperative. The interconnect resistance can be sharply reduced by changing the interconnect material from Al to Cu. However, there are many Cu-specific problems to be solved (for example, diffusion of Cu, the adhesion of Cu to an insulating film, and a technique for forming a Cu film), and reliable Cu interconnects or plugs cannot be easily achieved.
FIGS. 2A through 2D are cross-sectional views illustrating process steps in a known method for forming a Cu interconnect. As illustrated in FIG. 2A, a trench 110 is formed in an interlayer dielectric 101 formed on a substrate (or an insulating film) 100, and a barrier film 102 made of, for example, a TiN film is formed to cover the interlayer dielectric 101 and the inner walls of the trench 110. This barrier film 102 serves to prevent diffusion of Cu and improve the adhesion of Cu. In order to improve the adhesion of the barrier film 102, the barrier film 102 is subjected to plasma treatment for improving the quality of the barrier film 102.
Next, as illustrated in FIG. 2B, a Cu seed film 103 is formed, for example, by a PVD (physical vapor deposition) method to cover the barrier film 102, and then, as illustrated in FIG. 2C, an interconnect material, Cu 104, is embedded in the trench 110 by electrolytic plating using the Cu seed film 103 as an electrode. Subsequently, the embedded Cu 104 is annealed, and then, as illustrated in FIG. 2D, part of the Cu 104 formed on the interlayer dielectric 101 is planarized, for example, by a CMP (chemical mechanical polishing) method. In this manner, an interconnect or plug is configured by embedding the Cu 104 in the trench 110.
Meanwhile, in the known method, the width and aspect ratio of the trench 110 and other factors may cause the trench 110 to be insufficiently filled with Cu 104, leading to generation of voids. The reason for this is considered as follows. For example, when the degree to which a region of the barrier film 102 located on the sidewall of the trench 110 is modified by plasma treatment is insufficient, Cu atoms agglomerate on the region thereof which is located on the sidewall of the trench 110 and on which a thinner part of the Cu seed film 103 is formed by PVD. This reduces the amount of Cu electrodeposited on the region of the barrier film 102 located on the sidewall of the trench 110 by electrolytic plating of Cu, leading to generation of voids.
A method in which use of Cu doped with Al (for example, a Cu—Al alloy) as a material of a seed film 103 restrains voids from being generated due to the agglomeration of Cu atoms is disclosed in a patent document (Japanese Unexamined Patent Application Publication No. 2004-14626). It has been considered that the above-described method can be explained as follows. Al contained in the seed film 103 reacts with Ti in a barrier film 102 made of TiN, thereby producing a compound of Al3Ti. Consequently, the state of the seed film 103 bound with the barrier film 102 and thus the state of the surface of the seed film 103 are changed, resulting in a reduction of the agglomerated Cu atoms.